Semiconductor device having a gate structure surrounding a fin

Details Semiconductor device having a gate structure surrounding a fin Semiconductor device having a gate structure surrounding a fin

2005-11-01

2005-11-01

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S406000

Reexamination Certificate

active

06960804

ABSTRACT:
A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.

REFERENCES:
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6764884 (2004-07-01), Yu et al.
patent: 6768158 (2004-07-01), Lee et al.
patent: 6812119 (2004-11-01), Ahmed et al.
patent: 2003/0042531 (2003-03-01), Lee et al.
patent: 2003/0113970 (2003-06-01), Fried et al.
patent: 2004/0075121 (2004-04-01), Yu et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 200 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFet,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. Appl. No. 10/348,758 filed Jan. 23, 2003 entitled “Germanium Mosfet Devices and Methods for Making Same,” Judy Xilin An et al., 22 page specification, 29 sheets of drawings.

Affiliated with

Also associated with

Rating

Semiconductor device having a gate structure surrounding a fin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having a gate structure surrounding a fin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a gate structure surrounding a fin will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3499418