Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-07
2005-06-07
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06904572
ABSTRACT:
A computer-implemented method for designing a semiconductor integrated circuit, which optimizes the propagation delay of a path from a signal input terminal (source) to a signal output terminal (sink) on the same net, includes: calculating the ratio of the total sum of a gate input load capacitance to the wiring capacitance of the path from the source to the sink as a process variation sensitivity relating to the capacitance component of the path to be designed from the source to the sink, based on a circuit design information of a gate level of the semiconductor integrated circuit to be designed; and optimizing the process variation sensitivity relating to the capacitance component of each path in order that the process variation sensitivities relating to the capacitance components of all the paths are smaller than a reference value.
REFERENCES:
patent: 5235521 (1993-08-01), Johnson et al.
patent: 6550050 (2003-04-01), Hosono et al.
patent: 2001/0049814 (2001-12-01), Matsumoto et al.
patent: 10-125788 (1998-05-01), None
patent: 10-214941 (1998-08-01), None
Notice of Grounds for Rejection mailed on Jun. 8, 2004 corresponding to Japanese Patent Application No. 2002-057227 as received from the Japenese Patent Office.
DLA Piper Rudnick Gray Cary US LLP
Do Thuan
Kabushiki Kaisha Toshiba
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