Semiconductor device capable of avoiding latchup breakdown...

Details Semiconductor device capable of avoiding latchup breakdown... Semiconductor device capable of avoiding latchup breakdown...

2005-12-27

2005-12-27

Ngô, Ngân V. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257S379000

Reexamination Certificate

active

06979850

ABSTRACT:
A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

REFERENCES:
patent: 6864543 (2005-03-01), Kaneko et al.
patent: 2002/0063298 (2002-05-01), Wang
patent: 2005/0045964 (2005-03-01), Henmi et al.
patent: 60-74560 (1985-04-01), None
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patent: 5-152523 (1993-06-01), None
patent: 11-68053 (1999-03-01), None
patent: 2002-252333 (2002-09-01), None

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