Method for recognizing and avoiding etch-critical regions

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

06928627

ABSTRACT:
In a method for recognizing etch-critical regions, the critical regions are already determined in the layout under the processor control dependent on the fabrication-oriented rules and are automatically rectified in the existing layout, so that under-etchings are avoided in the following etching procedures.

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patent: 5885748 (1999-03-01), Ohnuma
patent: 5923563 (1999-07-01), Lavin et al.
patent: 6044007 (2000-03-01), Capodieci
patent: 6077310 (2000-06-01), Yamamoto et al.
patent: 6370441 (2002-04-01), Ohnuma
patent: 6609245 (2003-08-01), Liebmann et al.
patent: 2003/0046653 (2003-03-01), Liu
patent: 196 31 160 (1997-02-01), None
Handbuch der Leiterplattentechnik, vol. 2, Neu Verfahren, Neu Technologien, 1991, pp. 22-37.

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