Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-06
2005-12-06
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S128000
Reexamination Certificate
active
06973540
ABSTRACT:
In a multi-way cache, a method for selecting N ways available for replacement includes providing a plurality of rulesets where each one of the plurality of rulesets specifies N ways in the cache that are available for replacement (where N is equal to or greater than zero). The method further includes receiving an access address, and using at least a portion of the access address to select one of the plurality of rulesets. The selected one of the plurality of rulesets may then be used to select N ways in that cache that are available for replacement. One embodiment uses the high order bits of the access address to select a ruleset. An alternate embodiment uses at least a portion of the access address and a ruleset selector control register to select the ruleset. Yet another embodiment uses the access address and address range comparators to select the ruleset.
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PPC440CPU Core User's Manual: Jul. 18, 2002; pp 94-97; Jul. 18, 2002: pp 94-97; IBM.
Moyer William C.
Vaglica John J.
Chiu Joanna G.
Freescale Semiconductor Inc.
Hill Susan C.
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