Multi-processor system including a mode switching controller

Details Multi-processor system including a mode switching controller Multi-processor system including a mode switching controller

2005-02-15

2005-02-15

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S118000, C711S121000, C711S126000, C711S131000, C711S149000, C711S170000, C709S244000, C709S248000, C709S241000, C709S241000, C713S400000, C713S401000

Reexamination Certificate

active

06857052

ABSTRACT:
Any of the processors CPU1to CPUn turns the miss hit detecting signal line5to a low level upon detecting occurrence of a miss hit. In response, the mode switching controller2is notified of the occurrence of a miss hit and switches each of the processors CPU1to CPUn to the synchronous operation mode. Also, each command from each of the processors CPU1to CPUn is appended with a tag. When each of the processors CPU1to CPUn feeds the synchronization detecting signal line6with the tags which are identical as designated as a synchronous point, the operation of the processors can be switched to the non-synchronous operation mode by the mode switching controller2.

REFERENCES:
patent: 5220660 (1993-06-01), Yoshizawa et al.
patent: 5384906 (1995-01-01), Horst
patent: 5388242 (1995-02-01), Jewett
patent: 5860159 (1999-01-01), Hagersten
patent: 5968160 (1999-10-01), Saito et al.
patent: 6466988 (2002-10-01), Sukegawa et al.
patent: 20020083243 (2002-06-01), Van Huben et al.

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