Method for forming a ROM coding in a semiconductor device

Details Method for forming a ROM coding in a semiconductor device Method for forming a ROM coding in a semiconductor device

2005-08-23

2005-08-23

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S595000

Reexamination Certificate

active

06933217

ABSTRACT:
Disclosed is a method for manufacturing a semiconductor device. The source/drain impurity area is formed by using the open base characteristic, the ion implantation of high density impurities for connecting source/drain is performed, the first contact hole, the non-crystalline poly-silicon layer and the PMD layer are formed consecutively, the ion implantation is performed, and then the metal lines are formed. Therefore, the size of the chip is reduced as the coding is performed by using the first contact hole without any coding area, the damage to the semiconductor substrate is reduced and the leakage current is reduced as the first contact hole is formed before the PMD layer, the ON characteristic can be achieved by the reverse type ion implantation to the OFF characteristic, which is contrary to the case of a current ROM coding techniques, and the cutting of the metal line is minimized as the poly-silicon layer is formed under the metal line layer during the deposition of the metal lines.

REFERENCES:
patent: 5527730 (1996-06-01), Kayaoka et al.
patent: 6157069 (2000-12-01), Shin et al.
patent: 6207999 (2001-03-01), Wu
patent: 6221722 (2001-04-01), Lee
Masuoka et al.; “An 80 ns 1 Mbit MASK ROM with a New Memory Cell”; pp. 651-657; IEEE Journal of Solid-State Circuits vol. SC-19, No. 5 Oct. 1984.

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