Memory LSI failure analysis apparatus and analysis method...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C365S201000, C702S180000

Reexamination Certificate

active

06854080

ABSTRACT:
Provided are a device, method and storage medium, which, when a memory LSI defect analysis apparatus is used as a monitoring device to estimate reductions in yield, automatically interprets results, and calculates the period of distribution patterns and the mix rate of regular patterned defects. The total defect number of bits is found, and the factor f, is selected. The value of expected value functions, T(f), for the selected f is found, and if it is decided that regularly patterned defects are included, then regular pattern defect mix rate function MR(f) is calculated from number of bits, factor f, and the value of estimated value function T(f). If it is decided that it does not contain regularly patterned defects the regular patterned defect mix rate function MR(f) is assumed to be zero; and it is confirmed whether or not MR(f) has been found for every f.

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