Methods and arrangements for an enhanced scanable latch circuit

Details Methods and arrangements for an enhanced scanable latch circuit Methods and arrangements for an enhanced scanable latch circuit

2005-12-06

2005-12-06

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S114000, C326S016000, C714S726000

Reexamination Certificate

active

06972598

ABSTRACT:
Methods, and arrangements to enhance speed and reduce power consumption in a scanable latch circuit are disclosed. Embodiments include a wired-or circuit to facilitate independent paths for scan data and normal input data through the scanable latch circuit. In particular, to reduce delays related to gates between the input pin for the system clock and a normal input gate, dual, substantially independent paths are implemented: a scan path and a normal input path. Embodiments coordinate transmission of data from a normal input gate and a scan input gate to an output latch, a scan out pin, and/or combinational logic by incorporating buffers that isolate a wired-or node from either the scan input gate, the normal input gate, or both with a high impedance.

REFERENCES:
patent: 4780666 (1988-10-01), Sakashita et al.
patent: 5227674 (1993-07-01), Takahashi et al.
patent: 5233638 (1993-08-01), Moriwaki et al.
patent: 5248905 (1993-09-01), Kuo
patent: 5272397 (1993-12-01), Chen et al.
patent: 5349255 (1994-09-01), Patel
patent: 5656962 (1997-08-01), Banik
patent: 5689517 (1997-11-01), Ruparel
patent: 5925143 (1999-07-01), Gillis et al.
patent: 5938782 (1999-08-01), Kay
patent: 5973529 (1999-10-01), Chappell et al.
patent: 6075386 (2000-06-01), Naffziger
patent: 6240536 (2001-05-01), Mikan et al.
patent: 6271683 (2001-08-01), Horne et al.
patent: 6686775 (2004-02-01), Campbell

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