Dual-gate CMOS semiconductor device and dual-gate CMOS...

Details Dual-gate CMOS semiconductor device and dual-gate CMOS... Dual-gate CMOS semiconductor device and dual-gate CMOS...

2005-02-08

2005-02-08

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S350000, C257S371000

Reexamination Certificate

active

06853039

ABSTRACT:
A manufacturing method for a dual-gate CMOS semiconductor device that suppresses mutual diffusion of P type impurities and N type impurities in a gate electrode. An NMOS part and a PMOS part are formed on a semiconductor substrate. A polycrystalline silicon layer is formed on the NMOS part and the PMOS part, and consists of an N type impurity containing polycrystalline silicon layer and a P type impurity containing polycrystalline silicon layer. A first conductive layer is formed on the polycrystalline silicon layer so as to include a groove region, in which the first conductive layer is not formed, on a predetermined region including a boundary between the N type impurity containing polycrystalline silicon layer and the P type impurity containing polycrystalline silicon layer.

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