Process for fabricating a dual charge storage location...

Details Process for fabricating a dual charge storage location... Process for fabricating a dual charge storage location...

2005-10-25

2005-10-25

Wilson, Christian (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S260000, C257S261000, C257S315000, C257S316000, C257S317000

Reexamination Certificate

active

06958510

ABSTRACT:
A process for fabricating a dual charge storage location, electrically programmable memory cell, comprising: forming a first dielectric layer over a semiconductor material layer of a first conductivity type; forming a charge trapping material layer over the first dielectric layer; selectively removing the charge trapping material layer from over a central channel region of the semiconductor material layer, thereby leaving two charge trapping material layer portions at sides of the central channel region; masking the central channel region and selectively implanting dopants of a second conductivity type into the semiconductor material layer to form memory cell source/drain regions at sides of the two charge trapping material layer portions; forming a second dielectric layer over the charge trapping material layer; and forming a polysilicon gate over the second dielectric layer, the polysilicon gate being superimposed over the central channel region and the two charge trapping material layer portions.

REFERENCES:
patent: 5714412 (1998-02-01), Liang et al.
patent: 5923978 (1999-07-01), Hisamune
patent: 5949711 (1999-09-01), Kazerounian
patent: 6011725 (2000-01-01), Eitan
patent: 6271090 (2001-08-01), Huang et al.
patent: 6406960 (2002-06-01), Hopper et al.
patent: 6434053 (2002-08-01), Fujiwara
patent: 6492228 (2002-12-01), Gonzalez et al.
patent: 6538292 (2003-03-01), Chang et al.
patent: WO 01/17030 (2001-03-01), None

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