Pulse driven single bit line SRAM cell

Details Pulse driven single bit line SRAM cell Pulse driven single bit line SRAM cell

2005-02-08

2005-02-08

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S188000, C365S174000, C365S189011, C365S189030

Reexamination Certificate

active

06853578

ABSTRACT:
A single bit line, pulse-operated memory cell. The memory cell includes a first and second inverter, write access and feedback-control transistors, and read access transistor and read buffer transistors. The output of the first inverter is connected to the input of the second inverter and the output of the second inverter is connected to the input of the first inverter through the channel of the feedback-control transistor. The write access and feedback-control transistors are opposite types, and their gates are connected together so that when the feedback control transistor is on the write-access transistor is off and visa versa. Writing the cell thus avoids contending the with the on-transistor of the second inverter. The output of the cell is sensed by the gate of the buffer transistor and coupling the output of the buffer transistor through the read access transistor to the read output line.

REFERENCES:
patent: 5923593 (1999-07-01), Hsu et al.
patent: 6006339 (1999-12-01), McClure
patent: 6067253 (2000-05-01), Gotou
patent: 6108233 (2000-08-01), Lee et al.
patent: 6246386 (2001-06-01), Perner
patent: 6473334 (2002-10-01), Bailey et al.
patent: 6590812 (2003-07-01), Frey

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