Error correction with low latency for bus structures

Details Error correction with low latency for bus structures Error correction with low latency for bus structures

2005-12-20

2005-12-20

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S004110, C714S712000, C714S757000, C714S777000

Reexamination Certificate

active

06978416

ABSTRACT:
Correction and location information are determined from a number of data vectors. The location information comprises values determined from subsets of the data vectors. Two or more of the subsets have one or more data vectors in common, but also have one or more data vectors, in one or more of the subsets, that are not in other subsets. The subsets comprise groups of data vectors, and the groups of data vectors have a size that is a function of a power of two. Transmission codes are used on the data vectors and correction and location information. Received location information and determined location information are compared to determine a data vector having an error. Received correction information and determined correction information are compared to correct the data vector having the error. Failing optical lanes may be replaced efficiently by using a number of multiplexers coupled to electrical lanes and optical lanes.

REFERENCES:
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 5740186 (1998-04-01), Widmer
patent: 5784387 (1998-07-01), Widmer
patent: 6198413 (2001-03-01), Widmer
patent: 6496540 (2002-12-01), Widmer
U.S. Appl. No. 10/091,673, “DC-Balanced 7B/8B, 9B/10B, and Partitioned DC-Balanced 12/B/14B, 17B/20B, and 16B/18B Transmission Codes.”.
“Proposal for a Very Short Reach (VSR) OC-192/STM-64 Interface Based on Parallel Optics,” Optical Internetworking Forum (OIF), Los Angeles, CA, Contribution No. OIF-99, 120 (Oct. 19-20, 1999).

Affiliated with

Also associated with

Rating

Error correction with low latency for bus structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error correction with low latency for bus structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error correction with low latency for bus structures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3489712