Semiconductor memory

Details Semiconductor memory Semiconductor memory

2005-08-16

2005-08-16

Bonzo, Bryce P. (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S822000

Reexamination Certificate

active

06931565

ABSTRACT:
A semiconductor memory is configured such that it can be connected with a first and second timing generator. The semiconductor memory includes (a) a first register configured to communicate with a memory array and the first timing generator, to retrieve and to hold first data from the memory array at a first timing, (b) a logic gate configured to communicate with the memory array and the first register, to receive the first data from the first register and second data from the memory array after the first timing, so as to compare the first and second data with each other, so that it can provide a comparison result indicating whether or not the first and second data agree with each other, and (c) a second register configured to communicate with the logic gate and the second timing generator, to retrieve and to hold the comparison result at a second timing.

REFERENCES:
patent: 3703706 (1972-11-01), Ogura et al.
patent: 4245212 (1981-01-01), Cirimele
patent: 4653055 (1987-03-01), Micic et al.
Pilo, et al., “Design-for-Test Method for Stand-Alone SRAMS at 1Gb/s/pin and Beyond”, International Test Conference 2000 Proceedings, pp. 436-443.

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