Semiconductor integrated circuit including CMOS logic gate

Details Semiconductor integrated circuit including CMOS logic gate Semiconductor integrated circuit including CMOS logic gate

2005-12-27

2005-12-27

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S678000, C365S156000

Reexamination Certificate

active

06979870

ABSTRACT:
A semiconductor integrated circuit of an aspect of the present invention having a CMOS logic gate including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, has a first MOS transistor region in which the first MOS transistor is formed, and a 2ath MOS transistor region and a 2bth MOS transistor region, in each of which the second MOS transistor is formed, separately arranged to be in contact with a first side of said first MOS transistor region and a second side opposite to the first side.

REFERENCES:
patent: 5072286 (1991-12-01), Minami et al.
patent: 5444275 (1995-08-01), Kugishima et al.
patent: 10-275914 (1998-10-01), None
Hsindao Lu, et al., “A 1-M Bit SRAM on Simox Material”, Prodeedings 1993 IEEE International SOI Conference, 1993, pp. 182-183.
Kouichi Kumagai, et al., “A New SRAM Cell Design Using 0.35 μm CMOS/SIMOX Technology”, Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp. 174-175.
Jon M. Stern, et al., “Silicon-on-Insulator (SOI): A High Performance ASIC Technology”, IEEE 1992 Custom Integrated Circuits Conference, 1992 pp. 9.2.1-9.2.4.
Nobutaro Shibata, et al., “A 2-V 300-MHz 1-Mb Current-Sensed Double-Density SRAM for Low-Power 0.3-μm CMOS/SIMOX ASICs”, IEEE Journal of Solid-State Circuits, vol. 36, No. 10, 2001, pp. 1524-1537.
U.S. Appl. No. 10/452,284, filed Jun. 3, 2003, Fuse.
U.S. Appl. No. 10/914,128, filed Aug. 10, 2004, Ohta et al.

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