Fault management and recovery based on task-ID

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

Other Related Categories

C714S005110, C714S006130, C718S100000

Type

Reexamination Certificate

Status

active

Patent number

06851072

Description

ABSTRACT:
In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a processor and a memory. A plurality of program tasks is executed on the processor (800). The processor requests access to memory in response to executing the tasks (802). Some of these access requests are not directly or not straightforwardly linked with the current program counter (PC); for example, a write transaction going through a write buffer (808). An access error resulting form this type of transaction error is referred to as an imprecise abort. A task-id value is supplied along with the address during a deferred memory access and corresponds to the task-id of the task that initiated the memory access (802). If an error condition that prevents normal completion of the memory transaction is detected (806), then a recovery routine uses the task-id value provided with the memory transaction request to identify which program task requested the transaction (810, 812). The recovery routine can then resolve the problem or kill the identified task.

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patent: 5487154 (1996-01-01), Gunji
patent: 6219689 (2001-04-01), Mori
patent: 6253225 (2001-06-01), Nakahara et al.
patent: 6389447 (2002-05-01), Singh
patent: 6564311 (2003-05-01), Kakeda et al.

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