Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S314000

Reexamination Certificate

active

06969884

ABSTRACT:
Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.

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patent: 2001-168306 (2001-06-01), None
Peter VanDerVoom, et al., CMOS Shallow-Trench-Isolation to 50-nm Channel Widths, IEEE Transactions on Electron Devices, vol. 47, No. 6, Jun. 2000, pp. 1175-1182.

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