Method of fabricating flash memory cell

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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C438S734000

Reexamination Certificate

active

06972260

ABSTRACT:
A method of fabricating a flash memory cell is provided. The method includes providing a substrate and forming a patterned mask layer over the substrate. Using the patterned mask layer as an etching mask, the substrate is etched to form a trench. Thereafter, a first dielectric layer is formed over the substrate and then a first gate and a second gate is formed beside each sidewall of the trench. A first source/drain region is formed in the substrate at the bottom of the trench. A second dielectric layer is formed over the substrate and then a passivation layer is formed over the second dielectric layer. Afterwards, a portion of the passivation layer, the second dielectric layer and the first dielectric layer are removed. A third gate is formed in the trench and then the mask layer is removed. A third dielectric layer is formed on the substrate. Thereafter, a fourth and a fifth gate are formed beside the respective sidewall of the first gate and the second gate. A second source/drain region is formed in the substrate on each side of the fourth and the fifth gate.

REFERENCES:
patent: 5479368 (1995-12-01), Keshtbod
patent: 5640031 (1997-06-01), Keshtbod
patent: 5656544 (1997-08-01), Bergendahl et al.
patent: 6130453 (2000-10-01), Mei et al.
patent: 6153471 (2000-11-01), Lee et al.
patent: 6214667 (2001-04-01), Ding et al.

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