Semiconductor solid phase epitaxy damage control method and...

Details Semiconductor solid phase epitaxy damage control method and... Semiconductor solid phase epitaxy damage control method and...

2005-08-23

2005-08-23

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S300000

Reexamination Certificate

active

06933579

ABSTRACT:
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A raised source/drain layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. An amorphized shallow source/drain extension implanted region is formed in the raised source/drain layer and the semiconductor substrate therebeneath. The amorphized region is then recrystallized to form a shallow source/drain extension having residual recrystallization damage elevated into the raised source/drain layer.

REFERENCES:
patent: 4584026 (1986-04-01), Wu et al.
patent: 4659392 (1987-04-01), Vasudev
patent: 5336903 (1994-08-01), Ozturk et al.
patent: 5998271 (1999-12-01), Schwalke
patent: 6174791 (2001-01-01), Lin et al.
patent: 6187655 (2001-02-01), Wang et al.
patent: 2004/0245581 (2004-12-01), Tsuchiaki

Affiliated with

Also associated with

Rating

Semiconductor solid phase epitaxy damage control method and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor solid phase epitaxy damage control method and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor solid phase epitaxy damage control method and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3482879