Microprocessor cache design initialization

Details Microprocessor cache design initialization Microprocessor cache design initialization

2005-11-22

2005-11-22

Padmanabhan, Mano (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000, C711S145000

Reexamination Certificate

active

06968428

ABSTRACT:
Techniques are disclosed for initializing a representation of a cache in a microprocessor design under test. The cache representation includes a plurality of cache entries, each of which is uniquely referenced by an address-way pair. A test case includes a plurality of cache initialization records, each of which includes a cache entry reference and an initial cache entry value. Each cache entry reference includes an address identifier and a way identifier. An initializer reads the cache initialization records and uses the records which contain valid address-way pairs to initialize cache entries in the cache representation. The initializer then uses the remaining records, in which the way identifier is an invalid (e.g., null) value, to initialize cache entries in the cache representation. Valid way identifiers are selected for these records in a manner which ensures that cache entries are not initialized more than once.

REFERENCES:
patent: 5564034 (1996-10-01), Miyake
patent: 5586290 (1996-12-01), Hirai et al.
patent: 5987561 (1999-11-01), Witt et al.
patent: 6006317 (1999-12-01), Ramagopal et al.
patent: 6052697 (2000-04-01), Bennett et al.
patent: 6052698 (2000-04-01), Bennett et al.
patent: 6189068 (2001-02-01), Witt et al.
patent: 2002/0010839 (2002-01-01), Tirumala et al.
patent: 2002/0156970 (2002-10-01), Stewart
patent: 2001188766 (2000-01-01), None
patent: WO 00/68777 (2000-11-01), None
“Cache Mapping and Associativity,” Lay Networks (2002), http://www.laynetworks.com/users/w ebs/cs01—tutorial2.htm.
“The Fundamentals of Cache,” Paul Mazzucco, SystemLogic.Net (2002), http://www.systemlogic.net/articles/00/10/cache/index.php.

Affiliated with

Also associated with

Rating

Microprocessor cache design initialization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprocessor cache design initialization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor cache design initialization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3482444