Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2005-08-09
2005-08-09
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S233500, C365S230060
Reexamination Certificate
active
06928008
ABSTRACT:
The semiconductor memory device includes an address change circuit, which is programmable to change a column address, and a column selection circuit, which generates first and second column selection signals addressing columns in first and second portions of a memory array based on the received column address from the address change circuit. When at least one column addressed by the column address in both of the first and second portions of the memory array includes a defective cell, the address change circuit can be programmed to change the address so that defective cells are not addressed.
REFERENCES:
patent: 5305284 (1994-04-01), Iwase
patent: 5373471 (1994-12-01), Saeki et al.
patent: 5452252 (1995-09-01), Wada et al.
patent: 6567310 (2003-05-01), Einaga et al.
patent: 2004/0004866 (2004-01-01), Hidaka
patent: 10-0135680 (1998-01-01), None
Kim Kwang-Hyun
Lee Hi-Choon
LandOfFree
Semiconductor memory devices with data line redundancy... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory devices with data line redundancy..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory devices with data line redundancy... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3482293