Non-refresh four-transistor memory cell

Details Non-refresh four-transistor memory cell Non-refresh four-transistor memory cell

2005-02-08

2005-02-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S191000, C365S225000

Reexamination Certificate

active

06853579

ABSTRACT:
An exemplary four-transistor random access memory cell includes a first transistor of a first conductivity type having a gate coupled to a word line and a source coupled to a bit line, a second transistor of the first conductivity type having a gate coupled to a drain of the first transistor and a source coupled to receive a first voltage, a third transistor of a second conductivity type having a source coupled to a drain of the second transistor, a source coupled to receive a second voltage and a drain coupled to the drain of the first transistor, and a fourth transistor of the second type having a gate coupled to the drain of the first transistor, a source coupled to receive the second voltage and a drain coupled to the drain of the second transistor.

REFERENCES:
patent: 5640342 (1997-06-01), Gonzalez
patent: 6005796 (1999-12-01), Sywyk et al.

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