Mixed-voltage CMOS I/O buffer with thin oxide device and...

Details Mixed-voltage CMOS I/O buffer with thin oxide device and... Mixed-voltage CMOS I/O buffer with thin oxide device and...

2005-08-09

2005-08-09

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S058000, C327S534000

Reexamination Certificate

active

06927602

ABSTRACT:
A buffer circuit on a first chip coupled between a first circuit on the first chip and a second circuit on a second chip including a driver circuit comprising at least a first PMOS transistor and a second PMOS transistor, one of the source and drain of the second PMOS transistor being coupled to the substrate of the first PMOS transistor, wherein the second PMOS transistor is turned off when a first signal having a voltage level higher than a power supply voltage of the buffer circuit appears at the node, and a gate-tracking circuit coupled to provide a first bias and a second bias to the gate of the first PMOS transistor depending on the signal appearing at the node.

REFERENCES:
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patent: 6313672 (2001-11-01), Ajit et al.
Marcel J. M. Pelgrom and E. Carel Dijkmans, “A 3/5 V Compatible I/O Buffer,” IEEE Journal of Solid-State Circuits, vol. 30, No. 7, Jul. 1995, pp. 823-825.
M. Takahashi; T. Sakurai, K. Sawada, K. Nogami, M. Ichida, and K. Matsuda, “3.3V-5V Compatible I/O Circuit Without Thick Gate Oxide,” Proc. of IEEE Custom Integrated Circuits Conference, 1992, May pp. 23.3.1-23.3.4.
G. Singh and R. Salem, “High-Voltage Tolerant I/O Buffers With Low-Voltage CMOS Process,” IEEE Journal of Solid-State Circuits, vol. 34, No. 11, 1999, pp. 1512-1525, Nov. 1999.
Deng-Yuan Chen, “Design of a Mixed 3.3V and 5V PCI I/O Buffer,” Proc. of ASIC, 1996, pp. 336-339, no month.

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