Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-11-15
2005-11-15
Huynh, Andy (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000, C257S507000
Reexamination Certificate
active
06965147
ABSTRACT:
A semiconductor device includes a substrate, a semiconductor layer of a first conductivity type having a single-crystal structure, and a plurality of transistors each including a first gate electrode provided above the semiconductor layer with a first gate insulation film laid therebetween, a pair of impurity regions of a second conductivity type being provided in the semiconductor layer and each becoming a source or drain region, and a channel body of the first conductivity type provided in the semiconductor layer at a portion between these impurity regions. The device also includes a first gate line for common connection of the first gate electrodes of the transistors, a dielectric layer provided above the substrate in an extension direction of the first gate line, for supporting the semiconductor layer under the pair of impurity regions to thereby dielectrically isolate between the substrate and the semiconductor layer, a second gate electrode provided above the substrate in such a manner as to underlie the channel bodies of the transistors and oppose the channel bodies with a second gate insulation film laid therebetween, the second gate electrode having a gate length larger than a onefold value of a gate length of the first gate electrode and yet less than or equal to thrice the gate length, and a second gate line provided above the substrate along the extension direction of the first gate line while being placed between portions of the dielectric layer underlying the pair of impurity regions, the second gate line being for common connection of the second gate electrode.
REFERENCES:
patent: 6194289 (2001-02-01), Lee
patent: 6646305 (2003-11-01), Assaderaghi et al.
T. Ohsawa, et al., International Solid-State Circuits Conference, pp. 152, 153 and 154, “Memory Design Using One-Transistor Gain Cell On Soi”, 2002.
Huynh Andy
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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