EEPROM memory including an error correction system

Details EEPROM memory including an error correction system EEPROM memory including an error correction system

2005-02-08

2005-02-08

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C365S189050

Reexamination Certificate

active

06854083

ABSTRACT:
An electrically erasable and programmable memory includes a memory array having memory cells connected to word lines and bit lines. The bit lines are arranged in columns. The memory also includes read circuits connected to the bit lines and programming latches connecting the bit lines to a programming line. The memory includes a device to break the conductive paths connecting the memory cells of a column to the read circuits when data has been loaded into the latches of the column, without breaking the conductive paths that connect the latches of the column to the read circuits.

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Patent abstracts of Japan, vol. 2000, No. 02; Publication No. 11328981 dated Nov. 30, 1999 entitled “Semiconductor Memory and Regulator”. Applicant: Matsushita Electric IND Co. Ltd.

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