Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-08-02
2005-08-02
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S303000, C438S305000, C438S585000, C438S591000, C438S589000, C438S595000
Reexamination Certificate
active
06924237
ABSTRACT:
A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and silicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.
REFERENCES:
patent: 6159782 (2000-12-01), Xiang et al.
patent: 6210999 (2001-04-01), Gardner et al.
patent: 6380589 (2002-04-01), Krivokapic
D.A. Buchanan, et al., “80 nm poly-silicon gated n-FETs with ultra-thin Al2O3gate dielectric for ULSI applications”.
Ootsuka Fumio
Sakai Satoshi
Yamamoto Satoshi
Goudreau George A.
Renesas Technology Corp.
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