Method and apparatus for optimizing prefetching based on...

Details Method and apparatus for optimizing prefetching based on... Method and apparatus for optimizing prefetching based on...

2005-11-08

2005-11-08

Tran, Denise (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S171000, C711S213000

Reexamination Certificate

active

06963954

ABSTRACT:
Address based prefetch logic varies prefetching according to address values in read requests. The address based prefetch logic can vary how much data is initially read into a prefetch buffer or when a prefetch buffer is refilled to an initial prefetch amount. One advantage of the address based prefetch logic is that prefetching and prefetch buffer refill rates are tuned for particular application. This is important since the system controller ordinarily does not know how much data the master is requesting beyond the first data phase. The requested read address is used as a hint to determine how much prefetching needs to occur. Over prefetching wastes memory bandwidth, and potentially adds latency to other masters sharing common busses. Under prefetching may cause the system controller that is acting as a PCI target to terminate the master's read request, thus wasting PCI bandwidth, adding latency.

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patent: 2002/0042861 (2002-04-01), Kavipurapu

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