Automatic program restructuring to reduce average cache miss...

Details Automatic program restructuring to reduce average cache miss... Automatic program restructuring to reduce average cache miss...

2005-06-14

2005-06-14

Elmore, Stephen (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

C711S005000, C711S118000, C711S170000, C711S173000

Reexamination Certificate

active

06907509

ABSTRACT:
A method, a computer or computer program product for automatically restructuring a program having arrays in inner loops to reduce an average penalty incurred for bursty cache miss patterns by spreading out the cache misses. The method may be used separately or in conjunction with methods for reducing the number of cache misses. The method determines a padding required for each array according to a proportion of the cache line size, to offset the starting points of the arrays relative to the start of a cache line memory access address for each array. Preferably, the starting points of the arrays that induce bursty cache misses are padded so that they are uniformly spaced from one another.

REFERENCES:
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patent: 5854934 (1998-12-01), Hsu et al.
patent: 5903917 (1999-05-01), Douceur et al.
patent: 5943691 (1999-08-01), Wallace et al.
patent: 6041393 (2000-03-01), Hsu
patent: 782078 (1997-07-01), None

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