Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2005-12-06
2005-12-06
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S052000
Reexamination Certificate
active
06972981
ABSTRACT:
The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row. The memory chips have separate writing and reading clock signal inputs for receiving the clock signals and the clock signal lines are routed in at least one loop, via the memory chips, from the buffer chip to the end of each row and from there back to the buffer chip
REFERENCES:
patent: 6477614 (2002-11-01), Leddige et al.
patent: 6480948 (2002-11-01), Virajpet et al.
patent: 6654270 (2003-11-01), Osaka et al.
patent: 2002/0129215 (2002-09-01), Yoo et al.
Jakobs Andreas
Kuzmenka Maksim
Ruckerbauer Hermann
Dicke Billig & Czaja, PLLC
Dinh Son T.
Infineon - Technologies AG
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