Data storage device with overlapped buffering scheme

Details Data storage device with overlapped buffering scheme Data storage device with overlapped buffering scheme

2005-10-04

2005-10-04

Anderson, Matthew D. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S219000, C711S154000

Reexamination Certificate

active

06952762

ABSTRACT:
A data storage device is disclosed that, in response to a data output request, outputs stored data beginning with a selected output start address. The disclosed data storage device is characterized in that the selectable output start addresses exhibit such slight spacings from one another that the amount of data storable between neighboring output start addresses is smaller than the amount of data output in response to a data output request. As a result thereof, the plurality of accesses onto the data storage device can be reduced to a minimum.

REFERENCES:
patent: 4467443 (1984-08-01), Shima
patent: 5307321 (1994-04-01), Sasai et al.
patent: 0 217 232 (1987-04-01), None
patent: WO 95/22791 (1995-08-01), None
H.P. Messmer, “PC-Hardwarebuch” 5. Auflage, Addison-Wesley, (1997), pp. 55,56.
Intel, Microprocessor and Peripheral Handbook, vol. 1, Microprocessor (1988) p. 4-121.

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