Dynamic phase aligning interface

Details Dynamic phase aligning interface Dynamic phase aligning interface

2005-12-06

2005-12-06

Liu, Shuwang (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S372000, C375S354000, C370S503000, C370S419000

Reexamination Certificate

active

06973151

ABSTRACT:
According one embodiment, an apparatus and method are disclosed for a dynamic phase aligning input interface. In the embodiment, a first device provides data to a second device. According to the embodiment, the interface is counter clocked, the second device being clocked by a first clock signal and providing a second clock signal source to the first device for clocking the data. The first device transmits the second clock signal and the data to the second device, with the second clock signal being delayed by the period of time required for the second clock signal source to propagate through the first device. The second device detects the phase of the first clock signal and the second clock signal and modifies the phase of the second clock signal source to align the phase of the first clock signal and the phase of the second clock signal.

REFERENCES:
patent: 5526359 (1996-06-01), Read et al.
patent: 6219395 (2001-04-01), Pollack et al.
patent: 6725390 (2004-04-01), Liu et al.
patent: 2002/0071510 (2002-06-01), Drerup et al.

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