Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-06
2005-12-06
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S142000, C711S143000
Reexamination Certificate
active
06973544
ABSTRACT:
A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a data crossbar system which interconnects all nodes. The disclosure is applicable to multiprocessor computer systems which utilize system memory distributed over more than one node and snooping of data states in each node which utilizes memory local to that node. Global snooping is used to provide a single point of serialization of data tags. A central crossbar controller examines cache state tags of a given address line for all nodes simultaneously and issues an appropriate reply back to a node requesting data while generating other data requests to any other node in the system for the purpose of maintaining cache coherence and supplying the requested data. The system utilizes memory local to each node by dividing such memory into local and remote categories which are mutually exclusive for any given cache line. The disclosure provides support for a third level remote cache for each node.
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Berg Thomas B.
Gilbert Bruce M.
Lovett Thomas D.
Moazzami Nasser
Raissinia Abdy
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