Processor virtualization mechanism via an enhanced...

Electrical computers and digital data processing systems: input/ – Interrupt processing

Reexamination Certificate

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Details

C710S048000, C718S108000, C712S013000, C712S228000, C712S244000

Reexamination Certificate

active

06981083

ABSTRACT:
A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

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