Growing copper vias or lines within a patterned resist using...

Details Growing copper vias or lines within a patterned resist using... Growing copper vias or lines within a patterned resist using...

2005-06-14

2005-06-14

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S637000, C438S643000, C438S687000

Reexamination Certificate

active

06905950

ABSTRACT:
The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features in the inverse pattern image. The copper features can be coated with a diffusion barrier layer and a dielectric. The dielectric is polished to leave the dielectric filling the spaces between copper features. The invention provides copper lines and vias without the need for a dielectric or metal etching step. Another benefit of the invention is that lines widths can be increased by trimming the patterned coating prior to growing the copper features.

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International Search Report mailed Feb. 19, 2003; Related to PCT/US02/03021 filed Jan. 31, 2002.

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