Semiconductor memory device having redundant circuit and method

Details Semiconductor memory device having redundant circuit and method Semiconductor memory device having redundant circuit and method

1992-07-27

1994-08-30

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

053434293

ABSTRACT:
In a semiconductor memory device having a spare memory cell array and a spare column decoder and a spare row decoder as redundant circuits, redundancy detecting circuits for testing to see whether the redundant circuits are used or not after completion of the semiconductor memory device as a product are set so as to be capable of providing particular current signals or voltage signals, which indicate that the redundant circuits are used to predetermined external terminals, in response to an output signal at a predetermined logic level from a spare row decoder activating circuit or a spare column decoder activating circuit. When an external address signal is supplied to the semiconductor memory device, a signal at a logic level according to whether the redundant circuits are used or not is automatically latched in the redundancy detecting circuits in response to an output signal of the spare row decoder activating circuit or the spare column decoder activating circuit, so that it becomes unnecessary to set the state of electric connection in the redundancy detecting circuits according to whether the redundant circuits are used or not in manufacture.

REFERENCES:
patent: 4586170 (1986-04-01), O'Toole et al.
patent: 4866676 (1989-09-01), Crisp
patent: 4885721 (1989-12-01), Ratanosaka
patent: 4984205 (1991-01-01), Sugibayashi
patent: 5034925 (1991-07-01), Kato
patent: 5195099 (1993-03-01), Ueda

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