Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-12-27
2005-12-27
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S775000, C714S718000
Reexamination Certificate
active
06981199
ABSTRACT:
Method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.
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Lamarre Guy J.
Micro)n Technology, Inc.
TraskBritt
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