Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2005-02-22
2005-02-22
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S287000, C438S288000, C438S783000, C438S785000
Reexamination Certificate
active
06858444
ABSTRACT:
Integrated memory circuits, key components in thousands of electronic and computer products, have recently been made using ferroelectric memory transistors, which offer faster write cycles and lower power requirements than over conventional floating-gate transistors. One problem that hinders the continued down-scaling of conventional ferroelectric memory transistors is the vulnerability of their gate insulations to failure at thinner dimensions. Accordingly, the inventors devised unique ferroelectric gate structures, one of which includes a high-integrity silicon-oxide insulative layer, a doped titanium-oxide layer, a weak-ferroelectric layer, and a control gate. The doped titanium-oxide layer replaces a metal layer in the conventional ferroelectric gate structure, and the weak-ferroelectric layer replaces a conventional ferroelectric layer. These replacements reduce the permittivity mismatch found in conventional gate structures, and thus reduce stress on gate insulation layers, thereby improving reliability of ferroelectric memory transistors, particularly those with thinner gate insulation.
REFERENCES:
patent: 4161038 (1979-07-01), Wu
patent: 5403788 (1995-04-01), Nishida et al.
patent: 5424975 (1995-06-01), Lowrey
patent: 5541871 (1996-07-01), Nishimura et al.
patent: 5541872 (1996-07-01), Lowrey et al.
patent: 5579258 (1996-11-01), Adachi
patent: 5635433 (1997-06-01), Sengupta
patent: 5638318 (1997-06-01), Seyyedy
patent: 5677865 (1997-10-01), Seyyedy
patent: 5680344 (1997-10-01), Seyyedy
patent: 5744374 (1998-04-01), Moon
patent: 5751626 (1998-05-01), Seyyedy
patent: 5847423 (1998-12-01), Yamamichi
patent: 5847989 (1998-12-01), Seyyedy
patent: 5856688 (1999-01-01), Lee et al.
patent: 5905672 (1999-05-01), Seyyedy
patent: 5917746 (1999-06-01), Seyyedy
patent: 5969380 (1999-10-01), Seyyedy
patent: 5999439 (1999-12-01), Seyyedy
patent: 6004825 (1999-12-01), Seyyedy
patent: 6151241 (2000-11-01), Hayashi et al.
patent: 6177361 (2001-01-01), Gilton
patent: 6198119 (2001-03-01), Nabatame et al.
patent: 6242298 (2001-06-01), Kawakubo
patent: 6310373 (2001-10-01), Azuma et al.
patent: 6339238 (2002-01-01), Lim et al.
patent: 6372519 (2002-04-01), Gilton
patent: 6373743 (2002-04-01), Chen et al.
Cho, I. H., “Highly Reliable Dual Gate Oxide Fabrication by Reducing Wet Etching Time and Re-Oxidation for Sub-Quarter Micron CMOS Devices”,Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999),pp. 174-175.
Etzold, K. F., “Ferroelectric and Piezoelectric Materials”,The Electrical Engineering Handbook(computer file);CRCnetBASE, (1999), pp. 1-13.
Guo, X., “High Quality Ultra-thin TIO2/Si3N4 Gate Dielectric for Giga Scale MOS Technology”,Technical Digest of 1998 IEDM, (1998), pp. 377-380.
Han, B. M., “Chopping effect on the crystallinity of ZnO films prepared by a r.f. planar magnetron sputtering method”,Thin Solid Films, 338, (1999),pp. 265-268.
Ishiwara, H., “Proposal of a Novel Ferroelectric-Gate Field Effect Transistor with Seperated Functions for Data read-Out Data Storage”, Precision and Intelligence Laboratory, Tokyo Institute of Technology,pp. 222-223.
Kobayashi, K., “Mechanism of Photoinduced Charge Transfer in Co(Li)-Doped ZnO Film”,Japanese Journal of Applied Physics, 31, (1992),pp. L 1079-L 1082.
Matsuo, Kouji, et al., “Low Leakage TiO2 Gate Insulator formed by Ultrathin TiN Deposition and Low-Temperature Oxidation”,Japanese Journal of Applied Physics, vol. 39, No. 10, (Oct. 2000),5794-5799.
Nishino, J., “Preparation of Zinc Oxide Films by Low-Pressure Chemical Vapor Deposition Method”,Mat. Res. Soc. Proc, 363, (1995),pp. 219-224.
Onodera, A., “Dielectric Activity and Ferroelectricity in Piezoelectric Semiconductor Li-Doped ZnO”,Jpn. J. Appl. Phys., 35, (1996),pp. 5160-5162.
Onodera, A. , “Ferroelectric Properties in Piezoelectric Semiconductor Zn1-M O (M×Li, Mg)”,Jpn. J. Appl. Phys., 36, (1997),pp. 6008-6011.
Saito, Y., “High-Integrity Silicon Oxide Grown at Low-temperature by Atomic Oxygen Generated in High-Density Krypton Plasma”,Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999),pp. 152-153.
Suntola, T., “Atomic Layer epitaxy”,Thin Solid Films, 216, (1992), pp. 84-89.
Valentini, A., “Preparation and characterization of Li-doped ZnO films”,American Vacuum Society, (1991), pp. 286-289.
Vehkamaki, Marko, et al., “Growth of Sr TiO3 and BaTiO3 Thin Films by Atomic Layer Deposition”,Electrochemical and Solid-State Letters, vol. 2, No. 10, (Oct. 1999),504-506.
Ahn Kie Y.
Forbes Leonard
Micro)n Technology, Inc.
Nguyen Tuan H.
Schwegman Lundberg Woessner & Kluth P.A.
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