Semiconductor memory device capable of controlling potential...

Details Semiconductor memory device capable of controlling potential... Semiconductor memory device capable of controlling potential...

2005-06-07

2005-06-07

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S227000

Reexamination Certificate

active

06903962

ABSTRACT:
Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.

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“Dynamically Controllable DC Level Converter (DCLC) Technique to Reduce Power Dissipation, and Application to High-Speed, Low-Power Circuits”, Yoshinori Oka et al., Technical Report of IEICE, SDM2001-122, ICD2001-45, Aug., 2001, pp. 69-76.

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