Method and apparatus for performing extraction on an...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06925618

ABSTRACT:
The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. However, for the frequent complex extraction sub problems, machine learning is used to build models. Specifically, Support Vector Machines are constructed to extract the desired electrical characteristics. To build the Support Vector Machines, Experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point set is created by creating a critical input spanning set, adding training points from critical regions in the input space, and adding training points from frequently encountered profile cases. The training point set is then used to train the Support Vector Machine that will extract electrical characteristics for the extraction sub problem.

REFERENCES:
patent: 5901063 (1999-05-01), Chang et al.
patent: 5903469 (1999-05-01), Ho
Li et al., “Pre-extracting Support Vectors for Support Vector Machine”, Aug. 2000, IEEE Proceedings of 5thInternational Conference on Signal Processing, vol. 3, pp. 1432-1435.
Ruping, “Incremental Learning with Support Vector Machines”, Dec. 2001, IEEE Proceedings of International Conference on Data Mining, pp. 641-642.

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