Method for improving chip yields in the presence of via flaring

Details Method for improving chip yields in the presence of via flaring Method for improving chip yields in the presence of via flaring

2005-06-07

2005-06-07

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06904575

ABSTRACT:
The current invention provides a modification procedure that reduces errors in integrated circuits due to via shorts while at the same time avoiding the unnesting of the layout design and thereby permitting verification of the layout design by LVS testing tools. The current invention identifies if potentially shorting vias have electrically redundant paths and, if so, creates cloned cells of the original cell but void of the potentially shorting vias. The cloned cell is electrically comparable to the original cell. In addition, each instantiation of the original cell in the shapes data base is replaced with the cloned cell when electrical redundancy is present. Also, the number of vias removed can be minimized or maximized while, at the same time, all via electrical shorts are removed, depending on the design requirements.

REFERENCES:
patent: 5347465 (1994-09-01), Ferreri et al.
patent: 5798937 (1998-08-01), Bracha et al.
patent: 6247853 (2001-06-01), Papadopoulou et al.
patent: 6415421 (2002-07-01), Anderson et al.
patent: 6756242 (2004-06-01), Regan
patent: 2002/0100005 (2002-07-01), Anderson et al.
patent: 2003/0084418 (2003-05-01), Regan

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