Method for rapid estimation of wire delays and capacitances...

Details Method for rapid estimation of wire delays and capacitances... Method for rapid estimation of wire delays and capacitances...

2005-08-16

2005-08-16

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06931610

ABSTRACT:
A fast method of estimating capacitances and wire delays in an integrated circuit design is based on placement information such as that contained in a gate schematic net list from a logic synthesis tool. A simple tree topology called a spine tree is constructed to connect the pins of the net as an approximation of actual connections therein. Capacitance is extracted for this topology assuming a worst case scenario, and Elmore delays are computed for the wire delays based on the worst-case capacitances. The method takes linear time as a function of the number of pins in the net and is much faster than using a Steiner tree method in this context.

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Das et al., “Routing in ad hoc networks using a spine”, Proceedings of the Sixth International Conference on Computer Communications and Networks, Sep. 22, 1997, pp. 34-39.

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