Apparatus and method for implementing integrated circuit memory

Details Apparatus and method for implementing integrated circuit memory Apparatus and method for implementing integrated circuit memory

1995-05-09

1997-04-22

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365210, G11C 1300

Patent

active

056234481

ABSTRACT:
In order to select between normal memory components and redundant memory components in an integrated circuit memory device, a logic signal (ENABLE/DISABLE) indicative of the requirement to access the normal memory components or to access the redundant memory components is generated in response to an applied address signal group. When the logic signal has a first logic state, power from dynamic power distribution unit (35) is applied to the output stages (32) of the column addressing apparatus (11,32) activating the normal column conducting paths and power is withheld from the output stages (37) which would otherwise activate the redundant column conducting paths. When the logic signal (ENABLE/DISABLE) has a second logic state, power is applied to the output stages 37 activating the redundant column conducting paths and withheld from the output stages 32 which would otherwise activate the normal column conducting paths. By directly controlling the power applied to the output stages (32,37), the logical combination of control signal and other parameter-bearing signals is avoided, thereby resulting in a faster response to the changes in the logic signal.

REFERENCES:
patent: 5295114 (1994-03-01), Kobayashi
patent: 5307316 (1994-04-01), Takamae

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