Semiconductor memory device having duty cycle correction...

Details Semiconductor memory device having duty cycle correction... Semiconductor memory device having duty cycle correction...

2005-08-23

2005-08-23

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06934215

ABSTRACT:
A semiconductor memory device having a duty cycle correction circuit and an interpolating circuit interpolating a clock signal in the semiconductor memory device are disclosed. The semiconductor memory device comprises a duty cycle correction circuit, which receives an external clock, corrects the duty cycle of the external clock, and outputs the corrected duty cycle. The duty cycle correction circuit comprises a first delay locked loop that receives the external clock, inverts the external clock, synchronizes the external clock with the inverted external clock, and outputs the synchronized clock; a second delay locked loop that receives the inverted external clock, synchronizes the inverted external clock with the external clock and outputs the synchronized clock; an inverting circuit that inverts the output signal of the first delay locked loop; an interpolation circuit that interpolates the output signal of the inverting circuit with the output signal of the second delay locked loop, and outputs the interpolated signal; and a control circuit that controls the interpolation circuit in response to the clock frequency information of the external clock.

REFERENCES:
patent: 6535040 (2003-03-01), Jung et al.
patent: 6677792 (2004-01-01), Kwak
patent: 6737927 (2004-05-01), Hsieh
patent: 6765421 (2004-07-01), Brox et al.
patent: 6859081 (2005-02-01), Hong et al.
patent: 2004/0041609 (2004-03-01), Lin
patent: 2002-42469 (2002-02-01), None
patent: 2000-0043233 (2000-07-01), None
English language abstract of Korean Publication No. 2000-0043233.
English language abstract of Japanese Publication No. 2002-42469.

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