Cache coherency mechanism using arbitration masks

Details Cache coherency mechanism using arbitration masks Cache coherency mechanism using arbitration masks

2005-11-01

2005-11-01

Lane, Jack (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S147000, C709S213000, C709S238000

Reexamination Certificate

active

06961825

ABSTRACT:
A distributed processing system includes a cache coherency mechanism that essentially encodes network routing information into sectored presence bits. The mechanism organizes the sectored presence bits as one or more arbitration masks that system switches decode and use directly to route invalidate messages through one or more higher levels of the system. The lower level or levels of the system use local routing mechanisms, such as local directories, to direct the invalidate messages to the individual processors that are holding the data of interest.

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Patterson et al., Computer Architecture A Quantitative Approach, Second Edition 1996 (First Edition 1990) pp. ix-xii and 654-685, Morgan Kaufmann Publishers, Inc., San Francisco, California.

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