Self-aligned trench isolation method and semiconductor...

Details Self-aligned trench isolation method and semiconductor... Self-aligned trench isolation method and semiconductor...

2005-10-11

2005-10-11

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000

Reexamination Certificate

active

06953973

ABSTRACT:
A method according to some embodiments of the invention includes forming a first gate pattern on a first region of a semiconductor substrate. The first gate pattern is formed to have a first gate insulating layer pattern, a first lower gate conductive layer pattern and a gate etching stopper layer pattern which are sequentially stacked. A second gate pattern is formed on a second region spaced apart from the first region to define a border region between the first and second regions. The second gate pattern is formed to have a second gate insulating layer pattern and a second lower gate conductive layer pattern, which are sequentially stacked. Thus, some embodiments may prevent two different gate conductive layers from overlapping with each other in the border region. Accordingly, semiconductor memory devices according to some embodiments of the invention do not have undesired active regions formed in the border region.

REFERENCES:
patent: 4495025 (1985-01-01), Haskell
patent: 5576226 (1996-11-01), Hwang
patent: 6596608 (2003-07-01), Saito
patent: 6780715 (2004-08-01), Jeong
patent: 2002/0016041 (2002-02-01), Boo et al.
patent: 2000-195969 (2000-07-01), None
patent: 2003-0003062 (2003-01-01), None
English language abstract of Japanese Publication No. 2000-195969.
English language abstract of Korean Publication No. 2003-0003062.

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