Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2005-06-14
2005-06-14
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Testing
C365S226000, C365S189090
Reexamination Certificate
active
06906971
ABSTRACT:
A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.
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Iwai Hidetoshi
Miyazawa Kazuyuki
Nakamura Masayuki
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nguyen Tan T.
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