Method for forming multiple fins in a semiconductor device

Details Method for forming multiple fins in a semiconductor device Method for forming multiple fins in a semiconductor device

2005-03-29

2005-03-29

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S587000, C438S399000, C438S696000

Reexamination Certificate

active

06872647

ABSTRACT:
A method of forming multiple fins in a semiconductor device includes forming a structure having an upper surface and side surfaces on the semiconductor device. The semiconductor device includes a conductive layer located below the structure. The method also includes forming spacers adjacent the structure and selectively etching the spacers and the conductive layer to form the fins. The fins may be used in a FinFET device.

REFERENCES:
patent: 5942787 (1999-08-01), Gardner et al.
patent: 6110837 (2000-08-01), Linliu et al.
patent: 6159820 (2000-12-01), Park
patent: 6225201 (2001-05-01), Gardner et al.
patent: 6271113 (2001-08-01), Yoon et al.
patent: 6362057 (2002-03-01), Taylor et al.
patent: 6391753 (2002-05-01), Yu
patent: 6391782 (2002-05-01), Yu
patent: 6475869 (2002-11-01), Yu
patent: 6479343 (2002-11-01), Hwang et al.
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6509253 (2003-01-01), Yu
patent: 6642090 (2003-11-01), Fried et al.
patent: 6664173 (2003-12-01), Doyle et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 6787439 (2004-09-01), Ahmed et al.
patent: 6815268 (2004-11-01), Yu et al.
patent: 20030006410 (2003-01-01), Doyle
patent: 20030027059 (2003-02-01), Schweeger
patent: 20030054623 (2003-03-01), Weimer et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.

Affiliated with

Also associated with

Rating

Method for forming multiple fins in a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming multiple fins in a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming multiple fins in a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3457484