Method for fabricating a chip scale package using wafer...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating

Reexamination Certificate

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C438S113000, C438S462000, C438S465000, C438S612000, C438S613000

Reexamination Certificate

active

06900079

ABSTRACT:
Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

REFERENCES:
patent: 4610079 (1986-09-01), Abe et al.
patent: 4670088 (1987-06-01), Tsaur et al.
patent: 5143865 (1992-09-01), Hideshima et al.
patent: 5496775 (1996-03-01), Brooks
patent: 5554887 (1996-09-01), Sawai et al.
patent: 5703406 (1997-12-01), Kang
patent: 5824569 (1998-10-01), Brooks et al.
patent: 5834843 (1998-11-01), Mori et al.
patent: 5844779 (1998-12-01), Choi
patent: 5867417 (1999-02-01), Wallace et al.
patent: 5908317 (1999-06-01), Heo
patent: 5933713 (1999-08-01), Farnworth
patent: 5950070 (1999-09-01), Razon et al.
patent: 5969426 (1999-10-01), Baba et al.
patent: 5977641 (1999-11-01), Takahashi et al.
patent: 6020629 (2000-02-01), Farnworth et al.
patent: 6054772 (2000-04-01), Mostafazadeh et al.
patent: 6077380 (2000-06-01), Hayes et al.
patent: 6097098 (2000-08-01), Ball
patent: 6107164 (2000-08-01), Ohuchi
patent: 6137164 (2000-10-01), Yew et al.
patent: 6150717 (2000-11-01), Wood et al.
patent: 6153448 (2000-11-01), Takahashi et al.
patent: 6181569 (2001-01-01), Chakravorty
patent: 6208018 (2001-03-01), Ma et al.
patent: 6297553 (2001-10-01), Horiuchi et al.
patent: 6331450 (2001-12-01), Uemura
patent: 6368896 (2002-04-01), Farnworth et al.
patent: 6379999 (2002-04-01), Tanabe
patent: 6499216 (2002-12-01), Fjelstad
patent: 11-135663 (1999-05-01), None
patent: 2000-133669 (2000-05-01), None
Baliga, John, “Wafer-Level Packages to Include Solder Ball Support,” Semiconductor International, Nov. 2000, p. 58.

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