Semiconductor memory device and control method thereof

Details Semiconductor memory device and control method thereof Semiconductor memory device and control method thereof

2005-10-18

2005-10-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S185090, C365S189050, C365S189120, C365S191000, C365S222000

Reexamination Certificate

active

06956777

ABSTRACT:
There are intended to provide a semiconductor memory device capable of data access with higher speed and improvement of data transfer rate by shortening refresh operation cycle by stable low-current-consumption operation, and a control method of such a semiconductor memory device. In advance to the refresh operation mode signal M(I), control signal SW is outputted. Consequently, the switching sections select stored address bus Ladd from each storing section and stored-redundancy-judgment-result bus LJ and output address information subject to refresh operation to a word-line-driving-system circuit. After the address information from each storing section is outputted, a control signal LCH is outputted. As a result, an address switching section selects refresh address bys Add(I) subject to next refresh operation and each storing section stores address Add(I) fetched in an internal address bus IAdd and its redundancy judgment result RJ(I).

REFERENCES:
patent: 6118710 (2000-09-01), Tsuji
patent: 11-120790 (1999-04-01), None

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