Strained-channel multiple-gate transistor

Details Strained-channel multiple-gate transistor Strained-channel multiple-gate transistor

2005-02-15

2005-02-15

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S401000, C257S619000, C257S623000

Reexamination Certificate

active

06855990

ABSTRACT:
A multiple-gate semiconductor structure is disclosed which includes a substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces. The fin is subjected to a strain of at least 0.01% and is positioned vertically on the substrate; source and drain regions formed in the semi-conducting material of the fin; a gate dielectric layer overlying the fin; and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces of the fin overlying the gate dielectric layer. A method for forming the multiple-gate semiconductor structure is further disclosed.

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Geppert, The Amazing Vanishing Transistor Act, Oct. 2002, IEEE Spectrum, pp. 28-33.

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